1. Field of the Invention
The present invention relates generally to oxygen containing plasma etchable layers within microelectronics fabrications. More particularly, the present invention relates to methods for forming residue free patterned oxygen containing plasma etched layers within microelectronics fabrications.
2. Description of the Related Art
Microelectronics fabrications are formed from microelectronics substrates over which are formed patterned microelectronics conductor layers which are separated by microelectronics dielectric layers.
As microelectronics integration levels have increased and microelectronics device and conductor element dimensions have decreased, it has become increasingly common within the art of microelectronics fabrication to employ interposed between the patterns of narrow linewidth dimension and/or narrow pitch dimension patterned microelectronics conductor layers within microelectronics fabrications microelectronics dielectric layers formed of low dielectric constant dielectric materials. For the purposes of this disclosure, low dielectric constant dielectric materials are intended as dielectric materials having a dielectric constant of less than about 3.0. For comparison purposes, dielectric layers formed of conventional silicon oxide dielectric materials, silicon nitride dielectric materials or silicon oxynitride dielectric materials typically have dielectric constants in the range of from about 4.0 to about 5.0.
Microelectronics dielectric layers formed of low dielectric constant dielectric materials are desirable interposed between the patterns of narrow linewidth dimension and/or narrow pitch dimension patterned microelectronics conductor layers within microelectronics fabrications since such dielectric layers formed from such low dielectric constant dielectric materials provide dielectric layers through which there may be fabricated microelectronics fabrications with enhanced microelectronics fabrication speed, attenuated patterned microelectronics conductor layer parasitic capacitance and attenuated patterned microelectronics conductor layer cross-talk.
Low dielectric constant dielectric materials which may be employed for forming low dielectric constant microelectronics dielectric layers within microelectronics fabrications are typically materials with hydrogen and/or carbon content, such as but not limited to organic polymer spin-on-polymer dielectric materials (such as but not limited to polyimide organic polymer spin-on-polymer dielectric materials, poly (arylene ether) organic polymer spin-on-polymer dielectric materials and fluorinated poly (arylene ether) organic polymer spin-on-polymer dielectric materials), amorphous carbon dielectric materials (such as but not limited to amorphous carbon and fluorinated amorphous carbon), and silsesqiuoxane spin-on-glass (SOG) dielectric materials (such as but not limited to hydrogen silsesquioxane spin-on-glass (SOG) dielectric materials, carbon bonded hydrocarbon silsesquioxane spin-on-glass (SOG) dielectric materials and carbon bonded fluorocarbon silsesquioxane spin-on-glass (SOG) dielectric materials).
While organic polymer spin-on-polymer dielectric materials, amorphous carbon dielectric materials, and silsesquioxane spin-on-glass (SOG) dielectric materials are thus desirable within the art of microelectronics fabrication for forming low dielectric constant microelectronics dielectric layers within microelectronics fabrications, organic polymer spin-on-polymer dielectric materials, amorphous carbon dielectric materials, and silsesquioxane spin-on-glass (SOG) dielectric materials are not entirely without problems in forming low dielectric constant microelectronics dielectric layers within microelectronics fabrications. In particular, it has been observed that when forming vias through carbon and fluorine containing oxygen containing plasma etchable fluorinated poly (arylene ether) organic polymer spin-on polymer dielectric materials to reach contact layers or contact regions formed within microelectronics fabrications while employing oxygen containing plasma etch methods as are disclosed within related co-pending and co-assigned patent application Ser. No. 09/086,772 filed May 27, 1998, issued as U.S. Pat. No. 6,019,906 on Feb. 1, 2000 titled Hard Masking Method for Forming Patterned Oxygen Containing Plasma Etchable Layer, there is often formed upon the sidewalls of the vias residue layers, which are presumably fluoropolymer residue layers. Such residue layers are undesirable when formed upon the sidewalls of vias formed through carbon and fluorine containing dielectric layers such as but not limited to fluorinated poly (arylene ether) organic polymer spin-on-polymer dielectric layers since their presence often precludes forming within those vias fully functional or reliable conductor stud layers.
It is thus towards the goal of forming within advanced microelectronics fabrications while employing oxygen containing plasma etch methods patterned low dielectric constant microelectronics dielectric layers formed from oxygen containing plasma etchable dielectric materials formed of carbon and fluorine containing materials, with attenuated residue formation upon the sidewalls of those patterned low dielectric constant microelectronics dielectric layers, that the present invention is more specifically directed. In a more general sense, the present invention is also directed towards forming within advanced microelectronics fabrications while employing oxygen containing plasma etch methods patterned microelectronics layers (not necessarily patterned microelectronics dielectric layers) formed of oxygen containing plasma etchable materials formed of carbon and fluorine containing materials, with attenuated residue formation upon the sidewalls of those patterned microelectronics layers.
Consistent with that which is cited within related co-pending and co-assigned Ser. No. 09/086,772 filed May 27, 1998, issued as U.S. Pat. No. 6,019,906 on Feb. 1, 2000 various photolithographic and etch methods have been disclosed in the art of microelectronics fabrication for forming patterned microelectronics layers within microelectronics fabrications.
For example, Liu in ULSI Technology, C. Y. Chang et al., eds., McGraw-Hill (1996), pp. 446-47, discloses in general various methods for forming within integrated circuit microelectronics fabrications bordered and borderless stacked patterned conductor contact layers. Disclosed are both damascene and non-damascene methods for forming the bordered and borderless stacked patterned conductor contact layers.
Similarly, Korczynski, in xe2x80x9cLow-k dielectric integration cost modelling,xe2x80x9d Solid State Technology, October 1997, pp. 123-28, discloses in general various methods for forming patterned low dielectric constant dielectric layers interposed between the patterns of patterned conductor interconnection layers within microelectronics fabrications. Disclosed are standard patterned conductor metal interconnection formation and isolation methods and dual damascene patterned conductor metal interconnection formation and isolation methods.
In addition, Lin et al., in U.S. Pat. No. 5,246,883, discloses a method for forming a contact via structure through at least one dielectric layer within an integrated circuit microelectronics fabrication. The method employs at least the one dielectric layer having formed thereover a first buffer layer which in turn has formed thereupon a second buffer layer, where the second buffer layer has a higher isotropic etch rate in an isotropic etch method than the first buffer layer. By employing the isotropic etch method for etching the second buffer layer and at least a portion of the first buffer layer, followed by an anisotropic etch method for etching any remainder of the first buffer layer and at least the one dielectric layer, the taper of the sidewall of a via formed through at least the second buffer layer, the first buffer layer and the dielectric layer may be controlled.
Further, Moslehi, in U.S. Pat. No. 5,460,693, discloses a photolithography method for use in fabricating patterned integrated circuit microelectronics layers within integrated circuit microelectronics fabrications, where the photolithography method is undertaken employing dry processing methods only. The completely dry processing photolithography method employs a halogen doped silicon layer or a halogen doped silicon-germanium layer as a photosensitive layer from which is subsequently grown an oxide hard mask layer employed as an etch mask layer when etching a processable integrated circuit microelectronics layer formed below the halogen doped silicon layer or the halogen doped silicon-germanium layer.
Yet further, Havemann, in U.S. Pat. No. 5,565,384, discloses a method for forming within an integrated circuit microelectronics fabrication a self-aligned via through an inorganic dielectric layer to access a patterned conductor layer formed below the inorganic dielectric layer, where the patterned conductor layer has interposed at least partially between its patterns an organic containing dielectric layer. The patterned conductor layer and the organic dielectric layer are completely covered by the inorganic dielectric layer. The method employs an anisotropic etchant which is selective to the inorganic dielectric layer with respect to the organic dielectric layer, such that the organic dielectric layer serves as an etch stop layer when etching the self-aligned via through the inorganic dielectric layer, thus avoiding overetching of the organic dielectric layer.
Still yet further, Shoda, in U.S. Pat. No. 5,529,953, discloses a method for forming within an integrated circuit microelectronics fabrication a void free patterned contiguous interconnection and contact stud layer within a dielectric layer having formed therein an interconnection trench contiguous with but at a different level than a contact via. The method employs forming upon the floor of the interconnection trench a first material which exhibits a first incubation time for forming the patterned contiguous interconnection and contact stud layer thereupon. The method also employs forming upon the floor of the contact via a second material which exhibits a second incubation time for forming the patterned contiguous interconnection and contact stud layer thereupon, where the first incubation time is greater than the second incubation time.
Moreover, Ohsaki, in U.S. Pat. No. 5,677,243, discloses a method for forming an interconnection stud layer within an interconnection via within a dielectric layer within an integrated circuit, where the interconnection via is conventionally formed employing a single etch method while employing a pair of patterned photoresist etch mask layers sequentially overlying the dielectric layer. The method employs a sacrificial organic interconnection via filling layer filled within the interconnection via subsequent to a first etch method within a pair of etch methods, such that the pair of etch methods may be undertaken with separate patterned photoresist layers and thus provide the interconnection stud layer and interconnection via of maximum width.
Finally, Lee et al., in U.S. Pat. No. 5,654,240, discloses a method for forming a patterned conductor contact layer contacting a semiconductor substrate within an integrated circuit microelectronics fabrication, while avoiding trenching within the semiconductor substrate when etching the patterned conductor contact layer from a corresponding blanket conductor contact layer formed contacting the semiconductor substrate. The method employs: (1) a first patterned conductor layer formed upon a patterned dielectric layer formed upon the semiconductor substrate, where the first patterned conductor layer does not contact the semiconductor substrate; and (2) a second patterned conductor layer patterned to terminate upon the first patterned conductor layer while contacting the first patterned conductor layer and the semiconductor substrate.
In addition to that which is cited within related co-pending and co-assigned patent application, Shan et al., in U.S. Pat. No. 5,514,247, discloses a plasma etch method for forming a via through a dielectric layer within a semiconductor integrated circuit microelectronics fabrication, where there is attenuated formation of a metalpolymer residue layer upon a sidewall of the via. The plasma etch method employs within the dielectric layer plasma etchant gas composition an etchant gas which volatilizes a metal which would otherwise form the metal-polymer layer.
Desirable in the art of microelectronics fabrication are oxygen containing plasma etch methods for forming patterned low dielectric constant microelectronics dielectric layers formed from oxygen containing plasma etchable dielectric materials which are formed of carbon and fluorine containing materials, with attenuated residue formation upon the sidewalls of those patterned low dielectric constant microelectronics dielectric layers. More particularly desirable within the art of microelectronics fabrication are plasma etch methods for forming patterned microelectronics layers (not necessarily patterned microelectronics dielectric layers) formed of oxygen containing plasma etchable materials which are formed of carbon and fluorine containing materials, with attenuated residue formation upon the sidewalls of those patterned microelectronics layers.
It is towards the foregoing objects that the present invention is both generally and more specifically directed.
A first object of the present invention is to provide an oxygen containing plasma etch method for forming within a microelectronics fabrication a patterned microelectronics layer formed from an oxygen containing plasma etchable material formed from a carbon and fluorine containing material.
A second object of the present invention is to provide a method in accord with the first object of the present invention, where the patterned microelectronics layer is formed with attenuated residue formation upon a sidewall of the patterned microelectronics layer.
A third object of the present invention is to provide a method in accord with the first object of the present invention or the second object of the present invention, where the oxygen containing plasma etchable material is a low dielectric constant dielectric material.
A fourth object of the present invention is to provide a method in accord with the first object of the present invention, the second object of the present invention, or the third object of the present invention, which method is readily commercially implemented.
In accord with the objects of the present invention, there is provided by the present a method for forming a patterned layer within a microelectronics fabrication. There is first provided a substrate employed within a microelectronics fabrication. There is then formed over the substrate an oxygen containing plasma etchable layer, where the oxygen containing plasma etchable layer is formed of a carbon and fluorine containing material. There is then formed over the oxygen containing plasma etchable layer a mask layer. There is then etched through use of an oxygen containing plasma etch method the oxygen containing plasma etchable layer to form a patterned oxygen containing plasma etched layer. The oxygen containing plasma etch method employs an etchant gas composition comprising an oxygen containing etchant gas and a fluorine containing etchant gas.
There is provided by the present invention an oxygen containing plasma etch method for forming within a microelectronics fabrication a patterned microelectronics layer formed from an oxygen containing plasma etchable material which is formed from a carbon and fluorine containing material, where the patterned microelectronics layer is formed with attenuated residue formation upon a sidewall of the patterned microelectronics layer. The method of the present invention realizes the foregoing object by employing when forming the patterned microelectronics layer an etchant gas composition employing in addition to an oxygen containing etchant gas a fluorine containing etchant gas. While the mechanism through which incorporation of a fluorine containing etchant gas in conjunction with an oxygen containing etchant gas when forming a patterned oxygen containing plasma etched microelectronics layer formed from a carbon and fluorine containing material provides the patterned oxygen containing plasma etched microelectronics layer with attenuated residue formation upon its sidewall is not entirely clear, it is nonetheless clear that there may be attenuated the formation of the residue layer upon the sidewall of the patterned oxygen containing plasma etched layer when employing when forming the oxygen containing plasma etched layer the fluorine containing etchant gas in addition to the oxygen containing etchant gas.
The method of the present invention may be employed where the oxygen containing plasma etchable layer formed from the carbon and fluorine containing material is a low dielectric constant dielectric layer. The method of the present invention does not discriminate with respect to the nature of the oxygen containing plasma etchable material from which is formed a patterned oxygen containing plasma etched layer in accord with the method of the present invention. Thus, although the method of the present invention is most likely to provide value when the oxygen containing plasma etchable layer formed of the carbon and fluorine containing material is a low dielectric constant dielectric layer, the method of the present invention may also be employed when the oxygen containing plasma etchable layer is formed of a carbon and fluorine containing material other than a low dielectric constant dielectric material.
The method of the present invention is readily commercially implemented. The present invention employs methods and materials as are otherwise generally known in the art of microelectronics fabrication. Since it is the process ordering and process control within the present invention which provides the method of the present invention, rather than the existence of individual methods and materials employed within the method of the present invention which provides the method of the present invention, the method of the present invention is readily commercially implemented.